`timescale 100us/100us
module ctrl_tb (
    
);

reg             clk,rstn;
wire [2:0]      ew,sn;
ctrl ctrl(
     .ew(ew)
    ,.sn(sn)
    ,.clk(clk)
    ,.rstn(rstn)
);

initial begin
   clk = 1'b0;
   rstn = 1'b0;
 end

always  begin
    #20 rstn = 1'b1;
    #20 rstn = 1'b0;
    #20 rstn = 1'b1;
    #50000;
end

always  begin
  #5 clk = ~clk;
end
endmodule //ctrl_tb